1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly, to a non-volatile semiconductor memory device capable of electrically writing and erasing data.
2. Description of the Related Art
Recently, in the field of non-volatile semiconductor memory devices, a flash EEPROM which uses hot electron injection for writing and flash erasing (tunnel-current) for erasing has become important. Since a flash EEPROM uses a memory transistor which can be constituted by one single transistor, the cell size of this kind of flash EEPROM can be smaller, the capacity thereof can be easily enlarged in the future, costs thereof can be greatly reduced, and a flash EEPROM can substitute for a magnetic memory, such as a floppy disk.
FIG. 1 is a cross-sectional view showing a typical memory cell transistor included in a flash EEPROM. FIGS. 2A and 2B are views showing an operating condition of a conventional memory cell transistor. FIG. 2A shows a writing operation while FIG. 2B shows an erasing operation.
At first, as shown in FIG. 1, a source 102 and a drain 104 are formed in a silicon substrate 100. A first gate oxide film 108 is formed on a channel 106 positioned between the source 102 and the drain 104. A floating gate 110 is formed on the first gate oxide film 108, and a second gate oxide film 112 is formed on the floating gate 110.
In an ordinary flash memory having of a structure as stated above, an operating source voltage VCC (e.g. 5 V) and an erasing power source voltage VPP (e.g. 12 V) are required and this memory thus cannot operate using only a single operating power source, i.e., the source voltage VCC.
Specifically, a drain bias Vd and a gate bias Vg are respectively applied to the drain 104 and the control gate 114 so that a current flows between the drain 104 and the source 102 of the cell transistor to efficiently generate hot electrons near the drain 104. A portion of hot electrons thus generated is injected into the floating gate 110. In order to efficiently generate hot electrons and to complete a writing operation within a time period which is suitable for practical use, the drain bias Vd and the gate bias Vg must be set to voltages higher than an ordinary power source voltage VCC. For example, in case of a memory having a capacity equivalent to 1 megabit, the gate bias Vg, drain bias Vd, and source bias Vs are respectively set to 12 V, 6.5 V, and 0 V, as shown in FIG. 2A. In addition the chip has an operating source voltage VCC of 5 V.
Meanwhile, in an erasing operation, a source bias VS and a voltage of 0 V are respectively applied to the source and the control gate, with the drain kept opened, to eject electrons from the floating gate. This source bias Vs must be set to be higher than the source voltage VCC. For example, the source bias Vs of 12 V is used in conventional cases, as shown in FIG. 2B.
In a writing operation, a current of 0.5 mA is required per one memory transistor element, and for example, a current of 16 mA must be supplied when data is simultaneously written into 32 pieces of cell transistors.
In addition, since a high voltage is applied to the source, a leakage current generated by a band-to-band tunneling phenomena flows and this current amounts to 10 nA per unit cell, so that a large source current thereby flows. For example, a current of approximately 20 mA is required to block-erase data of 2 megabit cell transistors.
In order to realize operation using a single power source, there is a method in which a charge pump circuit is fabricated on a chip. However, in order to boost a source voltage VCC to a source bias Vs of 12 V in an erasing operation and to simultaneously supply a large current, a large area is required for a capacitor and this necessitates an enlargement of the chip size. For example, in case of using a charge pump circuit arranged in two stages, a capacitor having a size of 1.5 mm square is required when an oxide film having a film thickness of 30 nm is used to create a voltage of 12 V from a power source of 4.5 V. In this case, the chip size is therefore extremely large and is not suitable for practical use.
Presently, a DC-DC converter used only for boosting voltages is provided outside the chip to overcome the situation stated above.
As an attempt to realize operation using a single power source, there is a method of using a negative gate voltage when erasing data, to attain a gate bias Vg of -10 V and a source bias Vs equal to a source voltage of VCC.
FIGS. 3A and 3B are views showing operation of this kind of memory. FIG. 3A shows a state during a writing operation, and FIG. 3B shows a state in an erasing operation.
In these cases, a drain bias Vd of about 6.5 V required for writing data can be obtained simply by providing a charge pump circuit which boosts the source voltage VCC to a voltage equivalent to the drain bias. A time period required for the boosting is shortened and an area occupied by the capacitor can be reduced to be small.
However, in this method, since another source bias Vs required for erasing data is equal to the source voltage VCC (4.5 to 5 V), variation of the source voltage easily influences the source bias in erasing, and this results in a problem that the cell threshold voltage distribution after erasing data increases and leads to a disadvantage that the manufacturing yield and operation margin are degraded.